Schematic #313311, Rev. D JUMPER SETTINGS 313311 313311 313311 313311 JUMPER PINS -O1 -02 -03 -04 FUNCTION J100 4 2-3 2-3 1-2 1-2 Quadrature Clock Phasing J102 3 2-3 2-3 2-3 2-3 System Clock Source J103 4 2-3 2-3 2-3 2-3 FPU CS/BERR J104 3 1-2 1-2 1-2 1-2 CPU Clock Source J200 3 1-2 2-3 1-2 2-3 NTSC/PAL Select J151 3 2-3 2-3 1-2 1-2 Rom Timing J152 3 2-3 2-3 1-2 1-2 Rom Timing J180 3 2-3 2-3 2-3 2-3 A2000 ROM Compatibility Jumpers J181 3 2-3 2-3 2-3 2-3 A2000 ROM Compatibility Jumpers J350 3 1-2 1-2 1-2 1-2 Tick Clock Source J351 3 2-3 2-3 2-3 2-3 Disable DF1: (1-2 to enable) J352 3 2-3 2-3 2-3 2-3 Light Pen Source J481 3 2-3 2-3 2-3 2-3 VDE Scan Double Only Jumper J482 3 1-2 1-2 1-2 1-2 VDE PLL Loop Adjust J483 3 --- --- --- --- VDE Factory Test Points J851 3 1-2 1-2 2-3 2-3 RAM Controiler Speed Jumper J852 3 2-3 2-3 2-3 2-3 Dram Type (4 Mbit vs 1 Mbit) Notes: J150, J151: Rom Timing The rom timing circuit provides four different speed settings to match the output enable, and access timing of the system roms. To set the jumpers, determine the output enabie time, and access times for the roms you wish to use. The rom must have lower values than for the setting you select. System standard roms have Toe = 110 ns, and Tacc = 250 ns. CLK J151 J150 Toe (min) Tacc (min) 16 Mhz 2-3 2-3 157 ns 250 ns 16 Mhz 2-3 1-2 220 ns 312 ns 16 Mhz 1-2 2-3 282 ns 375 ns 16 Mhz 1-2 1-2 345 ns 437 ns 25 Mhz 2-3 2-3 90 ns 160 ns 25 Mhz 2-3 1-2 130 ns 200 ns 25 Mhz 1-2 2-3 170 ns 240 ns 25 Mhz 1-2 1-2 210 ns 280 ns J180,J181: Rom Compatibility Jumpers J180 J181 A2000/A500 ROMS: 1-2 1-2 A3000 ROMS: 2-3 2-3 J852: Ram Controller Compatibility Setting J852 Ramseys w/ 256Kx4 rams 2-3 Ramseys w/ 1Mx4 rams 1-2